1. Technical Field
The present invention relates to computer devices and more particularly, but not exclusively, to managing access to physical layer hardware.
2. Background Art
Conventional communication devices often operate with a protocol stack including a physical layer, a link layer and a protocol layer. A physical layer (PHY) includes analog components and, in many applications, operates to transfer data from an integrated circuit (IC) to a board, connector, cable or the like. Unfortunately, due to pin and die constraints, a system-on-chip (SoC) and other such ICs can only support a limited number of PHYs. These ICs tend to be particularly useful in mobile applications.
Certain PHY standards for power-constrained applications, such as various mobile PHY (M-PHY) specifications issued by the MIPI® Alliance, support operation with any of multiple protocols including Universal Flash Storage (UFS), SuperSpeed USB Inter-chip (SSIC), Low Latency Interface (LLI), Mobile Peripheral Component Interconnect Express (M-PCIe) and Third Generation MIPI® Camera Serial Interface (CSI-3). PHYs that conform to such standards usually support modes to implement different data rates, and tend to be heavily constrained with respect to power, clock and/or other resource management. PHYs conforming to such a standard have, to date, been limited to supporting only one protocol stack—and thus only a single protocol—due in part to the resource management constraints imposed by the standard.